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What is the disadvantage of a level triggered pulse?
constant pulse is to be maintained for a greater span of time
another interrupt may be generated if the low-level signal is not removed before the ISR is finished
it is difficult to produce
another interrupt may be caused if the signal is still low before the completion of the last instruction
another interrupt may be caused if the signal is still low before the completion of the last instruction
Quick Summary: Practice and solve "What is the disadvantage of a level triggered pulse?..." for Electrical - Microprocessor. The correct answer is Option D: another interrupt may be caused if the signal is still low before the completion of the last instruction. Detailed step-by-step solution, conceptual clarity, and formulas on Examoogle.
Answer:
Option **(d) **