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Which type of RAM does not required refreshing circuit?
Dynamic RAM
Static RAM
Both
None
Static RAM
Static RAM (SRAM) does not require a refreshing circuit because it uses a bistable latching circuit, typically consisting of 6 transistors per cell, to hold data. In contrast, Dynamic RAM (DRAM) stores data as a charge in a capacitor, which naturally leaks over time, necessitating periodic refreshing.
Static RAM (SRAM) does not require a refreshing circuit because it uses a bistable latching circuit, typically consisting of 6 transistors per cell, to hold data. In contrast, Dynamic RAM (DRAM) stores data as a charge in a capacitor, which naturally leaks over time, necessitating periodic refreshing.
TrefreshтАЛтЙИ0 тАФ Refresh time required for SRAM
Q=CтЛЕV тАФ Charge storage principle requiring refresh in DRAM
SRAM uses flip-flop configurations (typically 6T architecture) to maintain state. As long as power is supplied, the cross-coupled inverters continuously reinforce the logic state ('0' or '1'). Because it does not rely on capacitive charge storage, there is no decay process and thus no need for external hardware refresh cycles.
SRAM cells consist of a cross-coupled inverter pair.
Data is volatile and lost when power is removed, but stable while powered.
SRAM is significantly faster than DRAM due to the lack of refresh delays.
DRAM requires a periodic refresh cycle to prevent charge leakage loss.
Higher speed (lower access time)
No refresh circuitry complexity
Lower power consumption at low frequencies
Higher cost per bit
Lower storage density due to 6T cell size
Requires larger chip area
CPU Cache memory (L1, L2, L3)
High-speed registers
| Feature | DRAM | SRAM |
|---|---|---|
Refresh Needed | Yes | No |
Cell Architecture | 1 Transistor, 1 Capacitor | 6 Transistors |
DRAM uses a '1T-1C' structure which is compact but leaky, hence the refreshing.
Option A is incorrect because Dynamic RAM is defined specifically by its requirement to be refreshed.
B is correct тАФ Static RAM uses bistable flip-flop logic to retain state, eliminating the need for periodic refreshing circuits required by DRAM.
In competitive exams, remember that DRAM is 'cheap and dense' (high capacity) while SRAM is 'fast and complex' (high performance).