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An ideal half-wave rectifier supplies a purely resistive load from a sinusoidal source. Let v L (t) be the load voltage and v D (t) be the diode voltage, measured with reference to the anode. Which of the following statements is always true over one complete cycle?
The average value of vD(t) becomes zero if the diode orientation is reversed.
The average values of vL(t) and vD(t) are equal in magnitude and opposite in sign.
The rms value of vD(t) equals the rms value of the source voltage.
The average value of vD(t) is zero because the diode conducts for half the cycle.
The average values of vL(t) and vD(t) are equal in magnitude and opposite in sign.
In a series circuit consisting of a source vsтАЛ(t), a diode vDтАЛ(t), and a load vLтАЛ(t), Kirchhoff's Voltage Law (KVL) dictates that the sum of voltages must equal the source voltage at any instant. Over one complete cycle, the average value of the sinusoidal source voltage is zero, leading to the condition where the average values of the load and diode voltages must be equal in magnitude and opposite in sign.
In a series circuit consisting of a source vsтАЛ(t), a diode vDтАЛ(t), and a load vLтАЛ(t), Kirchhoff's Voltage Law (KVL) dictates that the sum of voltages must equal the source voltage at any instant. Over one complete cycle, the average value of the sinusoidal source voltage is zero, leading to the condition where the average values of the load and diode voltages must be equal in magnitude and opposite in sign.
Think of a shared budget: if the source provides no net gain over a full cycle, whatever the load 'takes' (positive average), the diode component must 'surrender' (negative average) to keep the balance.
vsтАЛ(t)=vDтАЛ(t)+vLтАЛ(t) тАФ Kirchhoff's Voltage Law for the loop
VavgтАЛ=T1тАЛтИл0TтАЛv(t)dt тАФ Definition of average value over period T
According to KVL, vsтАЛ(t)=vDтАЛ(t)+vLтАЛ(t). Taking the integral over one full period T, we get T1тАЛтИл0TтАЛvsтАЛ(t)dt=T1тАЛтИл0TтАЛvDтАЛ(t)dt+T1тАЛтИл0TтАЛvLтАЛ(t)dt. Since the average value of a pure sinusoidal source over a cycle is zero, it follows that 0=VD(avg)тАЛ+VL(avg)тАЛ, implying VD(avg)тАЛ=тИТVL(avg)тАЛ.
The average value of a symmetric sinusoidal signal over a full cycle is zero.
For a half-wave rectifier, the load voltage vLтАЛ(t) is positive during the conduction half-cycle.
The diode voltage vDтАЛ(t) is zero during conduction and matches the source voltage during non-conduction, resulting in a negative average value.
KVL must hold instantaneously for every time t.
AC to DC power conversion
Signal rectification in electronics
Option D is incorrect because while the diode conducts for half a cycle, it blocks the other half where the full source voltage appears across it, resulting in a non-zero average.
Option C is incorrect because the RMS value of vDтАЛ(t) is VmтАЛ/2 for a half-wave rectifier, whereas the source RMS is VmтАЛ/2тАЛ.
B is correct тАФ By Kirchhoff's Voltage Law, the sum of average voltages around the loop must equal the average source voltage, which is zero for a sinusoid.
Always remember that the sum of average values of voltage drops across components in any closed loop is zero, regardless of the circuit nonlinearity.