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Which of the following statements are true about CPU cache memory? i. Cache memory is faster than main memory (RAM). ii. L1 cache is typically smaller and faster than L3 cache. iii. Cache memory stores frequently accessed data and instructions. iv. Cache memory is located outside the processor chip on the motherboard exclusively.
i, ii, and iii only
i, iii, and iv only
ii, iii, and iv only
i, ii, iii, and iv
i, ii, and iii only
Cache memory is a small, high-speed volatile memory component that bridges the speed gap between the CPU and main memory (RAM). Statements i, ii, and iii are true because cache utilizes Static RAM (SRAM) for faster access, employs a hierarchy where L1 is closest to the core (smallest, fastest), and relies on the principle of locality to store frequently accessed data.
Cache memory is a small, high-speed volatile memory component that bridges the speed gap between the CPU and main memory (RAM). Statements i, ii, and iii are true because cache utilizes Static RAM (SRAM) for faster access, employs a hierarchy where L1 is closest to the core (smallest, fastest), and relies on the principle of locality to store frequently accessed data.
Average┬аMemory┬аAccess┬аTime┬а(AMAT)=Hit┬аTime+(Miss┬аRate├ЧMiss┬аPenalty)
Cache operates based on the Principle of Locality (Temporal and Spatial). When the CPU requests data, it first checks the cache. A 'cache hit' allows rapid data retrieval, whereas a 'cache miss' requires fetching data from the slower main memory. The hierarchy (L1/L2/L3) balances access speed, capacity, and manufacturing cost.
L1 cache is integrated directly into the CPU core.
L3 cache is typically shared among all CPU cores.
Cache memory uses SRAM, while main memory uses DRAM.
Statement iv is false because modern cache memory is primarily integrated on-die within the processor package.
Reduces processor idle time waiting for data.
Significantly improves system performance by minimizing bus traffic.
High cost per bit compared to main memory.
Increases design complexity of the CPU chip.
Instruction prefetching.
Data buffering for high-speed computation.
Minimizing latency in high-frequency trading and scientific simulations.
Statement iv is false as most cache levels (L1, L2, and often L3) are integrated directly onto the processor die (on-chip).
SRAM (used in cache) does not require periodic refreshing like DRAM, contributing to its superior speed.
A is correct тАФ statements i, ii, and iii correctly describe the speed, hierarchical nature, and function of cache memory, while iv is incorrect as modern cache is integrated on the processor die.
Always remember the trade-off: As you move up the memory hierarchy from RAM towards CPU registers, the access speed increases, but the cost per byte and complexity also increase.
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